International Publications

  • 1999

  1. Soo H. Ong and Myung H. Sunwoo, “A fixed-point DSP (MDSP) chip for portable multimedia, ” IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences, vol. E82-A, no. 6, pp. 939-944, Jun. 1999.

  2. Hyun M. Chang and Myung H. Sunwoo, “Design of an area efficient Reed-Solomon decoder ASIC chip,” in Proc. Signal Processing Systems, 1999, pp. 578-585.

  3. Hyun J. Yoo, Soo H. Ong, and Myung H. Sunwoo, “The MDSP (Multimedia DSP) chip with an enhanced instruction set,” in Proc. IEEE International ASIC/ SoC Conference, 1999, pp. 98-102.

  4. H. J. Yoo, E. S. Ko, Soo. H. Ong and Myung H. Sunwoo, “A MDSP(Multimedia DSP) chip for portable applications,” in Proc. IEEE Asian Pacific ASIC Conference, 1999, pp.151-155.

  5. Hyun M. Chang and Myung H. Sunwoo, “VLSI design of a hardware efficient Reed-Solomon decoder,” in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 1999, pp. 565-568.

  6. Byung C. Lee and Myung H. Sunwoo, “Design of a high speed parallel Viterbi decoder for multimedia communications,” in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 1999, pp. 466-469.

  7. Hyun M. Chang and Myung H. Sunwoo, “A low complexity Reed-Solomon architecture using the Euclid's algorithm,” in Proc. International Symposium on Circuits and Systems , 1999, pp. 513-516.

  8. Soo H. Ong, Eck S. Ko, Hyun J. You, and Myung H. Sunwoo, “A MDSP(Multimedia DSP) chip for portable multi- media applications,” in Proc. International Symposium on Circuits and Systems, 1999, pp. 283-286.

  • 1998

  1. Myung H. Sunwoo and Soo H. Ong, “Implementation of a sliding memory plane image processor,” Journal of Parallel and Distributed Computing, Vol.55, pp. 236-248, Nov. 1998.

  2. Soo H. Ong, Myung H. Sunwoo, and Man P. Hong, “A Fixed-point multimedia DSP chip for portable multimedia services,” in Proc. Signal Processing Systems, 1998, pp. 94-102.

  3. Hyun M. Chang and Myung H. Sunwoo, “Implementation of a DSSS modem ASIC chip for wireless LAN,” in Proc. Signal Processing Systems, 1998, pp. 243-252.

  4. Seung W. Seo and Myung H. Sunwoo, “An enhanced template matching algorithm and its chip implementation,” in Proc. Signal Processing Systems, 1998, pp. 162-171.

  5. Hyun M. Chang, Soo H. Ong, and Myung H. Sunwoo, “Design and implementation of a programmable image processor,” in Proc. the 7th AJOU-FIT-NUST Joint Seminar, 1998, pp.45~54.

  6. Sung H. Yoon, Soo H. Ong, and Myung H. Sunwoo, “MDSP: The multimedia fixed-point DSP core,” in Proc. International Technical Conference on Circuits/Systems, Computers and Communications, 1998, pp.1297~1300.

  7. Hyun M. Chang, Soo H. Ong, Chang H. Lee and Myung H. Sunwoo, “Design of a scan line image processor chip,” in Proc. International Symposium on Circuits and Systems, 1998, pp. 425-428.

  8. Hyun M. Chang and Myung H. Sunwoo, “An efficient programmable 2-D convolver chip,” in Proc. International Symposium on Circuits and Systems, 1998, pp.345~348.

  • 1997

  1. Hyun M. Chang, Chang H. Lee, and Myung H. Sunwoo, “SliM-II: A linear array SIMD processor for real-time image processing,” in Proc. International Conference on Parallel and Distributed Systems , 1997, pp. 132-137.

  2. Soo H. Ong and M. H. Sunwoo, “A new cost-effective morphological filter chip,” in Proc. Signal Processing Systems, 1997, pp. 421-430

  3. Sung H. Yoon and M. H. Sunwoo, “Design of an efficient multiplierless FIR filter chip with variable-length taps,” in Proc. Signal Processing Systems, 1997, pp. 412-420.

  4. Se Y. Eun and Myung H. Sunwoo, “Design of a DSSS Wireless modem ASIC,” in Proc. the 4th International Workshop on Mobile Multimedia Communications, 1997, pp. 348-351.

  5. Hyun M. Chang, Soo H. Ong, Chang H. Lee, Myung H. Sunwoo, and Tai H. Choi, “A general purpose SliM-II image processor,” in Proc. 4th International Workshop on Computer Architecture for Machine Perception, 1997, pp. 253-259.

  6. Soo H. Ong and Myung H. Sunwoo, “A cost-effective morphological filter architecture,” in Proc. 4th International Workshop on Computer Architecture for Machine Perception, 1997, pp. 285-289.

  7. Soo H. Ong and Myung H. Sunwoo, “A hardware-effective and highly-scalable morphological filter chip,” in Proc. 5th International Conference on VLSI and CAD, 1997, pp. 364-366.

  8. Sung H. Yoon and Myung H. Sunwoo, “A hardware-effective multiplierless FIR filter chip with variable-length taps,” in Proc. 5th International Conference on VLSI and CAD, 1997, pp. 469-471.

  9. Su R. Ryu and Myung H. Sunwoo, “Design of an efficient high speed VLSI architecture for WLAN modem,” in Proc. the 40th Midwest Symposium on Circuits and Systems, Aug. 1997.

  10. Hyun M. Chang, Soo H. Ong, and Myung H. Sunwoo, “A linear array parallel image processor: SliM-II,” in Proc. 11th International Conference on Application-Specific Systems, Architectures and Processors, 1997, pp. 34-41.

  • 1996

  1. Soo H. Ong, Myung H. Sunwoo, and Tai Y. Choi, “An efficient morphological filter chip,” in Proc. the 5th AJOU-FIT-NUST Joint Seminar, 1996, pp. 174-182.

  2. Soo H. Ong, Su R. Ryu, Myung H. Sunwoo, and Sung G. Lee, “A parallel image processor chip for Real-time applications,” in Proc. International Symposium on Circuits and Systems, 1996, pp. 356-359.

  3. Hyun M. Chang, Myung H. Sunwoo, and Tai H. Cho, “Implementation of a SliM array processor,” in Proc. International Parallel Processing Symposium, 1996, pp. 771-775.

  • 1995

  1. Myung H. Sunwoo and Soo H. Ong, “The implementation of the SliM ASIC chip for parallel image processing,” in Proc. the 5th FIT-AJOU University Joint Seminar, 1995, pp. 101-107.

  2. Myung H. Sunwoo, Soo H. Ong, Byung D. Ahn, and Kyung W. Lee, “Design and implementation of a general purpose parallel image processor chip,” in Proc. International Conference on VLSI and CAD, 1995, pp. 29-32.

  3. Myung H. Sunwoo, Soo H. Ong, Byung D. Ahn, and Kyung W. Lee, “Design and implementation of parallel image processor chip for a SIMD array processor,” in Proc. International Conference on Application Specific Array Processors, 1995, pp. 66-75.

  • 1994

  1. Myung H. Sunwoo and J. K. Aggarwal, “FCM and FCHM multiprocessors for computer vision,” IEICE Trans. on Information and Systems, vol. E77-D, no. 11, Nov. 1994.

  2. Myung H. Sunwoo, Byung D. Ahn, Soo H. Ong, and Sung G. Lee, “Design of a SliM image processor for a SIMD parallel architecture,” in Proc. IEEE 7th International Conference on Parallel and Distributed Computing, 1994, pp. 312-313.

  3. Kyung W. Lee, Ji W. Jung, and Myung H. Sunwoo, “The architecture of a parallel for a SIMD computer,” in Proc. IASTED Int. conf. on parallel and Distributed Computing and Systems, 1994, pp. 177-180.

  • 1993

  1. Myung H. Sunwoo and J. K. Aggarwal, “A sliding memory plane array processor, ” IEEE Trans. on Parallel and Distributed Systems, vol. 4, pp. 601-612, Jun. 1993.

  2. Myung H. Sunwoo and J. K. Aggarwal, “FCM and FCHM multiprocessors for computer vision,” in Proc. Asian Conference on Computer Vision, 1993, pp. 710-714.

  3. Myung H. Sunwoo and S. H. Lee, “A SliM mesh-connected array processor with zero or little communication overhead,” in Proc. the 3rd FIT-AJOU University Joint Seminar, 1993, pp. 1-10.

  • 1992

  1. Myung H. Sunwoo and J. K. Aggarwal, “A flexibly coupled hypercube multiprocessor for high level vision,” Machine Vision and Applications, Springer-Verlag, vol. 5. pp. 127-138, Sep. 1992.

  2. Myung H. Sunwoo and S. Park, “Digital signal processors for digital cellular applications,” in Proc. Speech Tech. '92, 1992, pp. 147-155.

  • 1991

  1. Myung H. Sunwoo and S. Park, “Real-time implementation of the VSELP on a 16-bit DSP chip, ” IEEE Trans. on Consumer Electronics, vol. 37, no. 4, pp. 772-782, Nov. 1991.

  2. M. H. Sunwoo and J. K. Aggarwal, “VisTA - An Image Understanding Architecture, ” Parallel Architectures and Algorithms for Image Understanding, V. K. Prasanna Kumar ed.,Academic Press, 1991, pp. 121-154.

  3. Myung H. Sunwoo and S. Park, “A real-time implementation of VSELP on a 16-bit DSP chip,” in Proc. IEEE Workshop on Speech Coding for Telecommunications, 1991, pp. 76-77.

  4. Myung H. Sunwoo and S. Park, “A real-time implementation of key VSELP routines on a 16-bit DSP chip,” in Proc. IEEE International Conference on Consumer Electronics Rosemont, 1991, pp. 332-333.

  • 1990

  1. Myung H. Sunwoo and J. K. Aggarwal, “Flexibly coupled multiprocessors for image processing, ” Journal of Parallel and Distributed Computing, Academic Press, vol. 10, no. 2, pp. 115-129, Oct. 1990.

  2. Myung H. Sunwoo and J. K. Aggarwal, “A sliding memory plane array processor for low-level vision,” in Proc. the 10th International Conference on Pattern on Pattern Recognition, 1990, pp. 312-317.

  3. Myung H. Sunwoo and J. K. Aggarwal, “VisTA for a general purpose computer vision system,” in Proc. the 10th International Conference on Pattern Recognition, 1990, pp. 635-641.

  • 1988

  1. Myung H. Sunwoo and J. K. Aggarwal, “A sliding memory plane array processor,” in Proc. IEEE Second Symposium on Frontiers '88 Massively Parallel Computation, 1988, pp. 537-540.

  2. Myung H. Sunwoo and J. K. Aggarwal, “An integrated Vision Tri-Architecture (VisTA) system,” in Proc. DARPA Image Understanding Benchmark Workshop, Oct. 1988, pp.12-18.

  3. Myung H. Sunwoo and J. K. Aggarwal, “Flexibly coupled multiprocessors for image processing,” in Proc. 1988 International Conference on Parallel Processing, 1988, pp. 452-461.

  • 1987

  1. Myung H. Sunwoo, B. S. Baroody, and J. K. Aggarwal, “A parallel algorithm for region labeling,” in Proc. IEEECS Workshop on Computer Architecture for Pattern Analysis and Machine Intelligence, 1987, pp. 27-34.

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